Field of the Invention
The present invention relates to an image processing apparatus which includes a memory that caches management information associated with job processing, a control method for the image processing apparatus, and a storage medium.
Description of the Related Art
Conventionally, an image processing system such as a multifunction peripheral (MFP) is provided with a static random access memory (SRAM) as a backup memory device and a backup circuit using a battery, for dealing with data requiring backup. Such data requiring backup includes charging information and address information for performing data transmission.
On the other hand, a large-capacity flash memory has recently come into use as a storing unit for storing control programs and image data in the MFP.
Further, Japanese Patent Application Laid-Open No. 2011-096053 discusses realizing functions of the MFP by storing a system control program in the flash memory and storing an operation panel setting in the SRAM.
However, according to the technique discussed in Japanese Patent Application Laid-Open No. 2011-096053, a plurality of memory devices stores various data, so that the system becomes complex and the cost increases.
To solve such a problem, a new controller may be configured by moving the information conventionally stored in the SRAM to the flash memory and thus integrating the memory devices.
On the other hand, since an access size of the flash memory is different from that of the SRAM, data access by software using a conventional SRAM device interface (I/F) may lower the performance.
More specifically, the SRAM can be accessed in 1 byte unit according to the characteristics of the device. On the other hand, the flash memory can only be accessed in several kbyte units.
As a result, if the size of the data to be stored in the flash memory is small, a large amount of dummy data becomes accessed, and the data processing performance thus becomes lowered. To avoid such a problem, a control method may be performed in which direct data access is not performed with respect to the flash memory. The data is instead cached in a volatile high-speed memory such as a Double Data-Rate2 Synchronous Dynamic RAM (DDR2 SDRAM), and when update data reaches a predetermined amount, the flash memory is collectively accessed.
However, if the volatile device is used as a caching destination, the cached data may be lost when an unpredicted power discontinuity occurs.